与 arm-linux-gcc 一起使用的 C/C++ 目标的简单 makefile
声明：本页面是StackOverFlow热门问题的中英对照翻译，遵循CC BY-SA 4.0协议，如果您需要使用它，必须同样遵循CC BY-SA许可，注明原文地址和作者信息，同时你必须将它归于原作者（不是我）：StackOverFlow
原文地址: http://stackoverflow.com/questions/8731994/
Warning: these are provided under cc-by-sa 4.0 license. You are free to use/share it, But you must attribute it to the original authors (not me):
StackOverFlow
Simple makefile for C/C++ targets used with arm-linux-gcc
提问by Nicholas Kinar
I would like to cross-compile a simple program for ARM architecture using the arm-linux-gcc suite of compilers [arm-linux-gcc (Buildroot 2011.08) 4.3.6]. I've attempted to use a simple makefile for compiling C code, and another simple makefile for compiling C++ code. For example, my makefile for C code is reproduced below, but it does not create an ELF binary for running on my embedded system. The host system is x64 GNU Linux.
我想使用 arm-linux-gcc 编译器套件 [arm-linux-gcc (Buildroot 2011.08) 4.3.6] 交叉编译一个简单的 ARM 架构程序。我尝试使用一个简单的 makefile 来编译 C 代码，并使用另一个简单的 makefile 来编译 C++ 代码。例如，下面复制了我的 C 代码生成文件，但它不会创建在我的嵌入式系统上运行的 ELF 二进制文件。主机系统是 x64 GNU Linux。
Here is the listing of my very simple makefile for a C program:
这是我的 C 程序的非常简单的 makefile 列表：
CC=arm-linux-gcc
CFLAGS=-Wall
main: test.o
clean:
rm -f test test.o
The makefile reproduced above only creates an object file with extension .o, and does not create an ELF binary.
上面复制的 makefile 仅创建扩展名为 .o 的目标文件，并没有创建 ELF 二进制文件。
I've Googled for a good solution, but I can't seem to find one webpage showing example cross-compile ARM makefiles for both C and C++ programs. Perhaps an answer to this post could show such examples.
我在谷歌上搜索了一个很好的解决方案，但我似乎找不到一个网页显示 C 和 C++ 程序的交叉编译 ARM 生成文件示例。也许这篇文章的答案可以展示这样的例子。
采纳答案by Greg Hewgill
I tried your Makefileand changed the following:
我尝试了您的Makefile并更改了以下内容：
test: test.o
It worked after this changed and created a binary called test. It seems that there is some implicit rule that knows how to link whateverif one of its dependencies is whatever.o.
它在更改并创建了一个名为test. 似乎有一些隐含规则知道whatever如果其依赖项之一是whatever.o.
Another way is to list the rule explicitly:
另一种方法是明确列出规则：
main: test.o
$(CC) -o $@ $$
This uses the special macros $@(which means target) and $$(which means dependencies).
这使用了特殊的宏$@（表示target）和$$（表示依赖项）。
回答by thiton
Have a look at the GNU make manual (info make), Section 10.2. It has a catalogue of the implicit rules, i.e. the rules where you don't need to explicitly state the commands. Like @GregHewgill thought, the "Linking a single object file" implicit rule builds Nfrom N.o, but the name must match. Therefore, you can either name your executable like your object file, in which case
查看 GNU make 手册 ( info make), Section 10.2。它有一个隐含规则的目录，即不需要明确说明命令的规则。就像@GregHewgill 认为的那样，“链接单个对象文件”隐式规则N从构建N.o，但名称必须匹配。因此，您可以将您的可执行文件命名为您的目标文件，在这种情况下
test:
or (more standard because it defines the alltarget)
或（更标准，因为它定义了all目标）
all : test
completely suffice. You can also write out the rule explicitly, like Greg Hewgill also described. In this case, the standard rule is:
完全足够。您也可以明确地写出规则，就像 Greg Hewgill 也描述的那样。在这种情况下，标准规则是：
$(CC) $(LDFLAGS) N.o $(LOADLIBES) $(LDLIBS)
Include the LDFLAGS and LDLIBS in your Makefile, it makes life easier for users.
在你的 Makefile 中包含 LDFLAGS 和 LDLIBS，它使用户的生活更轻松。
(sic: I think LOADLIBES is really LOADLIBS, and the author missed the -o).
（原文如此：我认为 LOADLIBES 真的是 LOADLIBS，作者错过了-o）。
Overall, I'd recommend autoconfand automakeinstead of hand-rolling makefiles. Gives you a bunch of Makefile features for very little work.
总的来说，我建议使用autoconf和automake而不是手动滚动生成文件。为您提供大量 Makefile 功能，只需很少的工作。
