string Verilog 中的字符串操作
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String Manipulation in Verilog
提问by sjtaheri
I need to perform basic operations on strings like concatenation,replacement and comparison in my Verilog simulation. How could it be possible? Is there any built-in support?
我需要在 Verilog 模拟中对字符串执行基本操作，如连接、替换和比较。怎么可能？是否有任何内置支持？
Thanks in advance.
提前致谢。
回答by
There is no string datatype in Verilog however verilog does support string literals and using them as byte vectors. This is the example from the spec:
Verilog 中没有字符串数据类型，但是 verilog 确实支持字符串文字并将它们用作字节向量。这是规范中的示例：
module string_test;
reg [8*14:1] stringvar;
initial begin
stringvar = "Hello world";
$display ("%s is stored as %h", stringvar,stringvar);
stringvar = {stringvar,"!!!"};
$display ("%s is stored as %h", stringvar,stringvar);
end
endmodule
Since strings use the reg datatype you can use the normal operators to manipulate them, keeping in mind each character uses 8 bits.
由于字符串使用 reg 数据类型，您可以使用普通运算符来操作它们，请记住每个字符使用 8 位。
5.2.3.1 String operations
The common string operations copy, concatenate, and compare are supported by Verilog HDL operators. Copy is provided by simple assignment. Concatenation is provided by the concatenation operator. Comparison is provided by the equality operators. When manipulating string values in vector regs, the regs should be at least 8*n bits (where n is the number of ASCII characters) in order to preserve the 8-bit ASCII code.
5.2.3.1 字符串操作
Verilog HDL 运算符支持常见的字符串操作复制、连接和比较。复制是通过简单的分配提供的。串联由串联运算符提供。比较由相等运算符提供。在向量 regs 中处理字符串值时，regs 应至少为 8*n 位（其中 n 是 ASCII 字符的数量）以保留 8 位 ASCII 代码。
You'll have to write some tasks or functions if you need operations like searching.
如果您需要搜索等操作，则必须编写一些任务或函数。
回答by toolic
If you have access to a modern simulator which supports SystemVerilog syntax, there is a stringdata type. Strings can be concatenated and compared. Refer to the IEEE Std (1800-2009).
如果您可以访问支持 SystemVerilog 语法的现代模拟器，则有一种string数据类型。字符串可以连接和比较。请参阅 IEEE 标准 (1800-2009)。
回答by jmcneal
sjtaheri,
sjtaheri,
Reviving a dead thread, but I see this question come up, and there is a newer solution for it.
恢复一个死线程，但我看到这个问题出现了，并且有一个更新的解决方案。
svlib is a free, open-source library of utility functions for SystemVerilog. It includes file and string manipulation functions, full regular expression search/replace, easy reading and writing of configuration files, access to environment variables and wall-clock time, and much more. This project was presented at DVCon 2014.
svlib 是一个免费的、开源的 SystemVerilog 实用程序函数库。它包括文件和字符串操作功能、完整的正则表达式搜索/替换、轻松读写配置文件、访问环境变量和挂钟时间等等。该项目曾在 DVCon 2014 上展出。
