linux 内核 Makefile 中 obj-y += something/ 的含义是什么？
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Whats meaning of obj-y += something/ in linux kernel Makefile?
提问by Jeegar Patel
I understand the meaning of
我明白的意思
obj-$(CONFIG_USB) += usb.o
if CONFIG_USB is y then usb.o will be compiled. So now how to understand this
如果 CONFIG_USB 是 y，则将编译 usb.o。那么现在如何理解这个
obj-y += something/
采纳答案by Peter
Kernel Makefiles are part of the kbuildsystem, documented in various places on the web, for example http://lwn.net/Articles/21835/. The relevant excerpt is here:
内核 Makefile 是kbuild系统的一部分，记录在网络上的各个地方，例如http://lwn.net/Articles/21835/。相关摘录在这里：
--- 3.1 Goal definitionsGoal definitions are the main part (heart) of the kbuild Makefile. These lines define the files to be built, any special compilation options, and any subdirectories to be entered recursively.
The most simple kbuild makefile contains one line:
Example: obj-y += foo.o
This tell kbuild that there is one object in that directory named foo.o. foo.o will be build from foo.c or foo.S.
If foo.o shall be built as a module, the variable obj-m is used. Therefore the following pattern is often used:
Example: obj-$(CONFIG_FOO) += foo.o
$(CONFIG_FOO) evaluates to either y (for built-in) or m (for module). If CONFIG_FOO is neither y nor m, then the file will not be compiled nor linked.
--- 3.1 Goal definitions目标定义是 kbuild Makefile 的主要部分（核心）。这些行定义了要构建的文件、任何特殊的编译选项以及要递归输入的任何子目录。
最简单的 kbuild makefile 包含一行：
示例：obj-y += foo.o
这告诉 kbuild 在那个目录中有一个名为 foo.o 的对象。foo.o 将从 foo.c 或 foo.S 构建。
如果 foo.o 应构建为模块，则使用变量 obj-m。因此，经常使用以下模式：
示例：obj-$(CONFIG_FOO) += foo.o
$(CONFIG_FOO) 计算为 y（内置）或 m（模块）。如果 CONFIG_FOO 既不是 y 也不是 m，那么文件将不会被编译或链接。
So mmeans module, ymeans built-in (stands for yes in the kernel config process), and $(CONFIG_FOO) pulls the right answer from the normal config process.
所以m意味着模块，y意味着内置（在内核配置过程中代表是），而 $(CONFIG_FOO) 从正常的配置过程中提取正确的答案。
回答by étienne
Your question seems to be why a whole directory is added as a goal, the relevant part of the KConfig documentation is:
您的问题似乎是为什么要添加整个目录作为目标，KConfig 文档的相关部分是：
--- 3.6 Descending down in directories
A Makefile is only responsible for building objects in its own
directory. Files in subdirectories should be taken care of by
Makefiles in these subdirs. The build system will automatically
invoke make recursively in subdirectories, provided you let it know of
them.
To do so obj-y and obj-m are used.
ext2 lives in a separate directory, and the Makefile present in fs/
tells kbuild to descend down using the following assignment.
Example:
#fs/Makefile
obj-$(CONfIG_EXT2_FS) += ext2/
If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
the corresponding obj- variable will be set, and kbuild will descend
down in the ext2 directory.
Kbuild only uses this information to decide that it needs to visit
the directory, it is the Makefile in the subdirectory that
specifies what is modules and what is built-in.
It is good practice to use a CONFIG_ variable when assigning directory
names. This allows kbuild to totally skip the directory if the
corresponding CONFIG_ option is neither 'y' nor 'm'.
回答by Tulip
obj-y += something/
obj-y += 某物/
This means that kbuild should go into the directory "something". Once it moves to this directory, it looks at the Makefile in "something" to decide what objects should be built.
这意味着 kbuild 应该进入目录“something”。一旦它移动到这个目录，它就会在“某物”中查看 Makefile 来决定应该构建哪些对象。
It is analogous to saying- go to the directory "something" and execute "make"
这类似于说 - 转到目录“something”并执行“make”
