string 在 Verilog 中为连线分配 ASCII 字符
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Assign ASCII character to wire in Verilog
提问by Kevin Vermeer
I understand that you can declare a string in a Verilog test bench as follows:
我知道您可以在 Verilog 测试台中声明一个字符串，如下所示：
reg [8*14:1] string_value;
initial
string_value = "Hello, World!";
I can then do things with this string, like use $displayin a test bench to display it.
然后我可以用这个字符串做一些事情，比如$display在测试台中使用来显示它。
I haven't been successful in doing the same in a module when I flash it to my FPGA:
当我将模块闪存到我的 FPGA 时，我没有成功地在模块中做同样的事情：
reg [8*14:1] string_value;
always @(reset)
begin
string_value = "Hello, World!";
// Do stuff with string value
Even assigning a single value does not work:
即使分配单个值也不起作用：
reg [8:1] char_value;
always @(reset)
begin
char_value = "A";
if (char_value == 8'h41)
// Do stuff!
I want to shift the individual characters on an 8-bit bus to an LCD screen for display.
我想将 8 位总线上的单个字符转移到 LCD 屏幕上进行显示。
How can I work with strings in Verilog?
如何在 Verilog 中处理字符串？
采纳答案by Enze Chi
SystemVerilog should support string assignment as mentioned in spec:
SystemVerilog 应该支持规范中提到的字符串分配：
For example, to store the 12-character string "Hello world\n" requires a variable 8x12, or 96 bits wide.
bit [8*12:1] stringvar = "Hello world\n";
Not sure if the old verilog supports it or not.
不确定旧的 verilog 是否支持它。
回答by Stephen
You can assign a string to a register type. Anyone who says otherwise is wrong. You might want to make your registers 0' based for it to work properly. I've done this in real FPGAs and it works.
您可以将字符串分配给寄存器类型。任何说相反的人都是错误的。您可能希望将寄存器设为 0' 以使其正常工作。我已经在真正的 FPGA 中做到了这一点，并且它有效。
回答by ThomasD
Define an array of bytes, then assign ASCII to each array element:
定义一个字节数组，然后将 ASCII 分配给每个数组元素：
wire [7:0] foo [0:11];
assign foo[0] = "H";
assign foo[1] = "e";
assign foo[2] = "l";
assign foo[3] = "l";
assign foo[4] = "o";
assign foo[5] = " ";
assign foo[6] = "W";
assign foo[7] = "o";
assign foo[8] = "r";
assign foo[9] = "l";
assign foo[10] = "d";
assign foo[11] = "!";
You now have a constant with ASCII values in it that you can index into.
您现在有一个包含 ASCII 值的常量，您可以对其进行索引。
reg [7:0] data_out;
reg data_out_valid;
reg [3:0] some_index;
:
// pushing data onto a bus
data_out <= foo[some_index];
data_out_valid <= 1'd1;
some_index <= some_index + 4'd1;
With appropriate index checking and control that should work.
适当的索引检查和控制应该可以工作。
回答by Rafi
This works for me:
这对我有用：
reg [8*16:1] line1data = "Hello, World! ";
Both in simulation and on a Spartan-3E FPGA
在仿真和 Spartan-3E FPGA 上
回答by jay
output [8*14:1]string_value1;
reg [8*14:1]string_value1;
always @ (posedge BIWEn)
if (BIWEn==1'b1 ||BIREn==1'b1)
begin:START_STATE_WRITE
psW=idleW; //psW is Present State Write
string_value1= "IDLE";
end
![test bench] (c:\pictures)
回答by toolic
Strings seem to work in a module for me:
字符串对我来说似乎在一个模块中工作：
module tb;
reg [8:1] char_value;
initial begin
char_value = "A";
$display("%h", char_value);
if (char_value == 8'h41) begin
$display("match");
end else begin
$display("no match");
end
end
endmodule
/*
Prints out:
41
match
*/
What doesn't work for you?
什么对你不起作用？
The stringdata type was introduced into the SystemVerilog standard in 2005 (refer to IEEE 1800-2005 or 1800-2009).
该string数据类型于 2005 年引入 SystemVerilog 标准（参考 IEEE 1800-2005 或 1800-2009）。
