C语言 Makefile编译多个C程序？
声明：本页面是StackOverFlow热门问题的中英对照翻译，遵循CC BY-SA 4.0协议，如果您需要使用它，必须同样遵循CC BY-SA许可，注明原文地址和作者信息，同时你必须将它归于原作者（不是我）：StackOverFlow
原文地址: http://stackoverflow.com/questions/5950395/
Warning: these are provided under cc-by-sa 4.0 license. You are free to use/share it, But you must attribute it to the original authors (not me):
StackOverFlow
Makefile to compile multiple C programs?
提问by Sarah
This is an incredibly simple question, but I'm new to makefiles. I am trying to make a makefile that will compile two independent programs:
这是一个非常简单的问题，但我是 makefile 的新手。我正在尝试制作一个可以编译两个独立程序的 makefile：
program1:
gcc -o prog1 program1.c
program2:
gcc -o prog2 program2.c
All the examples online go into way more details than I need and are confusing! All I really want it to do is to run the two gcclines. What am I doing wrong?
网上的所有例子都比我需要的更详细，而且令人困惑！我真正想要它做的就是运行这两gcc行。我究竟做错了什么？
回答by cnicutar
Do it like so
这样做
all: program1 program2
program1: program1.c
gcc -o program1 program1.c
program2: program2.c
gcc -o program2 program2.c
You said you don't want advanced stuff, but you could also shorten it like this based on some default rules.
你说你不想要高级的东西，但你也可以根据一些默认规则像这样缩短它。
all: program1 program2
program1: program1.c
program2: program2.c
回答by hmofrad
Pattern ruleslet you compile multiple c files which require the same compilation commands using makeas follows:
模式规则允许您编译多个需要相同编译命令的 c 文件，make如下所示：
objects = program1 program2
all: $(objects)
$(objects): %: %.c
$(CC) $(CFLAGS) -o $@ $<
回答by Robert
############################################################################
# 'A Generic Makefile for Building Multiple main() Targets in $PWD'
# Author: Robert A. Nader (2012)
# Email: naderra at some g
# Web: xiberix
############################################################################
# The purpose of this makefile is to compile to executable all C source
# files in CWD, where each .c file has a main() function, and each object
# links with a common LDFLAG.
#
# This makefile should suffice for simple projects that require building
# similar executable targets. For example, if your CWD build requires
# exclusively this pattern:
#
# cc -c $(CFLAGS) main_01.c
# cc main_01.o $(LDFLAGS) -o main_01
#
# cc -c $(CFLAGS) main_2..c
# cc main_02.o $(LDFLAGS) -o main_02
#
# etc, ... a common case when compiling the programs of some chapter,
# then you may be interested in using this makefile.
#
# What YOU do:
#
# Set PRG_SUFFIX_FLAG below to either 0 or 1 to enable or disable
# the generation of a .exe suffix on executables
#
# Set CFLAGS and LDFLAGS according to your needs.
#
# What this makefile does automagically:
#
# Sets SRC to a list of *.c files in PWD using wildcard.
# Sets PRGS BINS and OBJS using pattern substitution.
# Compiles each individual .c to .o object file.
# Links each individual .o to its corresponding executable.
#
###########################################################################
#
PRG_SUFFIX_FLAG := 0
#
LDFLAGS :=
CFLAGS_INC :=
CFLAGS := -g -Wall $(CFLAGS_INC)
#
## ==================- NOTHING TO CHANGE BELOW THIS LINE ===================
##
SRCS := $(wildcard *.c)
PRGS := $(patsubst %.c,%,$(SRCS))
PRG_SUFFIX=.exe
BINS := $(patsubst %,%$(PRG_SUFFIX),$(PRGS))
## OBJS are automagically compiled by make.
OBJS := $(patsubst %,%.o,$(PRGS))
##
all : $(BINS)
##
## For clarity sake we make use of:
.SECONDEXPANSION:
OBJ = $(patsubst %$(PRG_SUFFIX),%.o,$@)
ifeq ($(PRG_SUFFIX_FLAG),0)
BIN = $(patsubst %$(PRG_SUFFIX),%,$@)
else
BIN = $@
endif
## Compile the executables
%$(PRG_SUFFIX) : $(OBJS)
$(CC) $(OBJ) $(LDFLAGS) -o $(BIN)
##
## $(OBJS) should be automagically removed right after linking.
##
veryclean:
ifeq ($(PRG_SUFFIX_FLAG),0)
$(RM) $(PRGS)
else
$(RM) $(BINS)
endif
##
rebuild: veryclean all
##
## eof Generic_Multi_Main_PWD.makefile
回答by Erik
all: program1 program2
program1:
gcc -Wall -o prog1 program1.c
program2:
gcc -Wall -o prog2 program2.c
回答by Master C
all: program1 program2
program1:
gcc -Wall -ansi -pedantic -o prog1 program1.c
program2:
gcc -Wall -ansi -pedantic -o prog2 program2.c
I rather the ansi and pedantic, a better control for your program. It wont let you compile while you still have warnings !!
我更喜欢 ansi 和 pedantic，更好地控制你的程序。当你仍然有警告时，它不会让你编译！！
回答by ern0
A simple program's compilation workflow is simple, I can draw it as a small graph: source -> [compilation] -> object [linking] -> executable. There are files(source, object, executable) in this graph, and rules(make's terminology). That graph is definied in the Makefile.
一个简单的程序的编译流程很简单，我可以把它画成一个小图：source -> [compilation] -> object [linking] -> executable。该图中有文件（源、对象、可执行文件）和规则（make的术语）。该图在Makefile 中定义。
When you launch make, it reads Makefile, and checks for changed files. If there's any, it triggers the rule, which depends on it. The rulemay produce/update further files, which may trigger other rulesand so on. If you create a good makefile, only the necessary rules(compiler/link commands) will run, which stands "to next" from the modified file in the dependency path.
当您启动 make 时，它会读取Makefile并检查更改的文件。如果有，它会触发规则，这取决于它。该规则可能会产生/更新更多文件，这可能会触发其他规则等。如果您创建了一个好的 makefile，则只会运行必要的规则（编译器/链接命令），即从依赖路径中修改后的文件“到下一个”。
Pick an example Makefile, read the manual for syntax (anyway, it's clear for first sight, w/o manual), and draw the graph. You have to understand compiler options in order to find out the names of the result files.
选择一个示例Makefile，阅读语法手册（无论如何，第一眼就很清楚，没有手册），然后绘制图形。您必须了解编译器选项才能找出结果文件的名称。
The make graph should be as complex just as you want. You can even do infinite loops (don't do)! You can tell make, which rule is your target, so only the left-standing fileswill be used as triggers.
制作图应该像您想要的那样复杂。你甚至可以做无限循环（不要做）！你可以告诉make，哪个规则是你的目标，所以只有左边的文件将被用作触发器。
Again: draw the graph!.
再次：绘制图形！。
回答by Misha Tavkhelidze
SRC = a.cpp b.cpp
BIN = $(patsubst %.cpp,%,$(SRC))
all: $(BIN)
clean:
rm -f $(BIN)
.PHONY: all clean
make allwill do:
make all会做：
c++ a.cpp -o a
c++ b.cpp -o b
If you set CXXand CXXFLAGSvariables makewill use them.
如果设置CXX和CXXFLAGS变量make将使用它们。
回答by M3RS
This will compile all *.cfiles upon maketo executables without the .cextension as in gcc program.c -o program.
这会将所有*.c文件编译make为没有.c扩展名的可执行文件，如gcc program.c -o program.
makewill automatically add any flags you add to CFLAGSlike CFLAGS = -g Wall.
make将自动添加您添加到CFLAGSlike 的任何标志CFLAGS = -g Wall。
If you don't need any flags CFLAGScan be left blank (as below) or omitted completely.
如果您不需要任何标志，CFLAGS可以将其留空（如下所示）或完全省略。
SOURCES = $(wildcard *.c)
EXECS = $(SOURCES:%.c=%)
CFLAGS =
all: $(EXECS)
