string vhdl：将向量转换为字符串
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vhdl: convert vector to string
提问by Sadik
How can I convert a std_logic vector, bit_vector or any other vector to string?
如何将 std_logic 向量、bit_vector 或任何其他向量转换为字符串？
Signal a,b : UNSIGNED(7 DOWNTO 0);
SIGNAL x,y,z : BIT_VECTOR(7 DOWNTO 0);
...
report "value: " & BIT_VECTOR'Image(x) severity note;
report "and this one: " & to_string(a) severity note;
This does not work, so how can I convert a vector to a string?
这不起作用，那么如何将向量转换为字符串？
回答by Botond Sándor Kirei
Here is a solution where the range of the std_logic_vector type variable does not have an impact on the return value:
这是一个解决方案，其中 std_logic_vector 类型变量的范围对返回值没有影响：
function to_string ( a: std_logic_vector) return string is
variable b : string (1 to a'length) := (others => NUL);
variable stri : integer := 1;
begin
for i in a'range loop
b(stri) := std_logic'image(a((i)))(2);
stri := stri+1;
end loop;
return b;
end function;
回答by PlayDough
The VHDL-2008 standard defines to_stringfor std_logic_vectorand std_ulogic_vector, as well as a variety of other types. It might be easiest to use the VHDL-2008 mode (most simulators support 2008 nowadays).
VHDL-2008 标准定义to_string了std_logic_vector和std_ulogic_vector以及各种其他类型。使用 VHDL-2008 模式可能是最简单的（现在大多数模拟器都支持 2008）。
回答by Brian Drummond
As you have discovered, the 'image attribute is only declared for scalar types, not arrays or records : the usual approach is to create one's own library of test utilities including to_stringor imagefunctions in a package at the start of a design, and use it throughout.
正如您所发现的，'image 属性仅针对标量类型声明，而不是数组或记录：通常的方法是在设计开始时在包中创建自己的测试实用程序库to_string或image函数，并在整个过程中使用它.
It would be perfectly possible to standardise a library of these, and you will probably find many potential "test utility" packages but none has really caught on well enough to deserve becoming a standard.
完全有可能对这些库进行标准化，您可能会发现许多潜在的“测试实用程序”包，但没有一个真正流行到足以成为标准的地步。
That being said, you might find the following package a useful starting point.
话虽如此，您可能会发现以下包是一个有用的起点。
It encapsulates a couple of custom datatypes with operations on them. No generics, but thanks to overloading, you can use the package as though its functions were generic. (You will notice that the function bodies are incomplete though!) Extending it and adding types is easy cut&paste for the most part; and it keeps a lot of clutter out of the main design.
它封装了几个带有操作的自定义数据类型。没有泛型，但由于重载，您可以使用该包，就好像它的功能是通用的一样。（虽然你会注意到函数体是不完整的！）扩展它和添加类型在大多数情况下很容易剪切和粘贴；并且它在主要设计中保持了很多混乱。
It may be better to separate out the type declns and the (testbench only) functions into two separate packages; Typesand Types_Test_Utils. Then Types is used throughout the design, while the test utilities are only exposed to the testbench.
最好将类型 declns 和（仅用于测试平台的）函数分离到两个单独的包中；Types和Types_Test_Utils。然后在整个设计中使用类型，而测试实用程序仅暴露给测试平台。
library IEEE;
use IEEE.numeric_std.all;
package Types is
subtype SmallNum is UNSIGNED(7 DOWNTO 0);
subtype BiggerNum is UNSIGNED(19 DOWNTO 0);
subtype Bits is BIT_VECTOR(7 DOWNTO 0);
-- and operations on these types
-- Simulate generic procedures using overloading
function to_string(N : Unsigned) return String;
function to_string(N : Bits) return String;
procedure eq_checker (name : string; sig,should : SmallNum; at : time);
procedure eq_checker (name : string; sig,should : Bits; at : time);
end Types;
package body Types is
function to_string(N : Unsigned) return String is
variable temp : string(1 to (N'length + 3)/4) := (others => 'x');
begin
-- not finished!
return temp;
end to_string;
function to_string(N : Bits) return String is
begin
return "hello";
end to_string;
procedure eq_checker(name : string; sig,should : SmallNum; at : time) is
begin
if (at = now) then
if sig = should then
report to_string(sig) & "has same value" severity note;
else
report to_string(sig) & "has not same value as " & to_string(should) severity note;
end if;
end if;
end procedure eq_checker;
procedure eq_checker(name : string; sig,should : Bits; at : time) is
begin
null;
end procedure eq_checker;
end Types;
And a simple tester for it...
还有一个简单的测试仪......
use Work.Types.all;
ENTITY tester IS
END tester;
ARCHITECTURE behavior OF tester IS
Signal a,b : SmallNum := X"AA";
Signal c : BiggerNum := X"ABCDE";
SIGNAL x,y : Bits := X"BB";
BEGIN
process(a,x) is
begin
report "value: " & to_string(X) severity note;
report "and this one: " & to_string(a) severity note;
report "this one too: " & to_string(c) severity note;
end process;
END;
回答by Jason
function slv_to_string ( a: std_logic_vector) return string is
variable b : string (a'length-1 downto 1) := (others => NUL);
begin
for i in a'length-1 downto 1 loop
b(i) := std_logic'image(a((i-1)))(2);
end loop;
return b;
end function;
:)
:)
回答by Sadik
package package_x is
subtype any_type is UNSIGNED(7 DOWNTO 0);
...
end package_x;
package body package_x is
procedure someprocedure (signal sig: in any_type) is
VARIABLE li : line;
file output : text open write_mode is "output";
begin
write(li, std_logic_vector(sig));
writeline(output, li);
end;
end package_x;
回答by Mathieu CAROFF
I ended up writing functions to do the std_logic_vector to string conversion.
我最终编写了函数来执行 std_logic_vector 到字符串的转换。
They are available in this gist, or below.
它们可以在这个 gist或下面找到。
util_str.vhd
util_str.vhd
-- Mathieu CAROFF
-- 2018-11-20
-- util_str.vhd
-- Utilitary functions to convert vectors to strings
-- Test:
-- ```bash
-- ghdl -a util_str.vhd
-- ghdl -r util_str_tb
-- ```
-- The answer from Jonathan Bromley to the toopic "std_logic_vector to string in hex format"
-- asked by Mad I.D. helped to write the functions below.
-- https://groups.google.com/forum/#!topic/comp.lang.vhdl/1RiLjbgoPy0
library ieee;
use ieee.std_logic_1164.all;
package util_str is
function bin (lvec: in std_logic_vector) return string;
function hex (lvec: in std_logic_vector) return string;
end package;
package body util_str is
function bin (lvec: in std_logic_vector) return string is
variable text: string(lvec'length-1 downto 0) := (others => '9');
begin
for k in lvec'range loop
case lvec(k) is
when '0' => text(k) := '0';
when '1' => text(k) := '1';
when 'U' => text(k) := 'U';
when 'X' => text(k) := 'X';
when 'Z' => text(k) := 'Z';
when '-' => text(k) := '-';
when others => text(k) := '?';
end case;
end loop;
return text;
end function;
function hex (lvec: in std_logic_vector) return string is
variable text: string(lvec'length / 4 - 1 downto 0) := (others => '9');
subtype halfbyte is std_logic_vector(4-1 downto 0);
begin
assert lvec'length mod 4 = 0
report "hex() works only with vectors whose length is a multiple of 4"
severity FAILURE;
for k in text'range loop
case halfbyte'(lvec(4 * k + 3 downto 4 * k)) is
when "0000" => text(k) := '0';
when "0001" => text(k) := '1';
when "0010" => text(k) := '2';
when "0011" => text(k) := '3';
when "0100" => text(k) := '4';
when "0101" => text(k) := '5';
when "0110" => text(k) := '6';
when "0111" => text(k) := '7';
when "1000" => text(k) := '8';
when "1001" => text(k) := '9';
when "1010" => text(k) := 'A';
when "1011" => text(k) := 'B';
when "1100" => text(k) := 'C';
when "1101" => text(k) := 'D';
when "1110" => text(k) := 'E';
when "1111" => text(k) := 'F';
when others => text(k) := '!';
end case;
end loop;
return text;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.util_str.all;
entity util_str_tb is
end entity;
architecture util_str_tb_arch of util_str_tb is
begin
process is
variable byte: std_logic_vector(12-1 downto 0) := "000001001111";
begin
report "bin " & bin(byte);
report "hex " & hex(byte);
wait;
end process;
end architecture;
